# Embedded Linux – Memory Management Line by line [1]– Intro to MMU

For embedded system, memory management varies from system to system, as you have your custom address space and custom peripheral devices and memory chips. Sometime, the porting of kernel may fail if the memory management is not carefully handled.

Years ago, uclinux was well-known as a linux operating system without MMU, which is more suitable for embedded systems back at that time. As FPGA has become more and more powerful, embedded OS can support MMU now. And for Linux running on Xilinx FPGA with microblaze or PPC, the MMU is required, as said in the documentation.

In this blog series, I am going to tell the story about memory management of Linux OS line by line. The story begins by introducing the MMU of microblaze.

### MMU of Microblaze on Xilinx FPGA\

Memory Management Unit (MMU) is a piece of hardware, which bonded closely with CPU (microblaze/PPC here) to provide memory management functionality for softwares, especially operating systems.

MMU can function in two modes:

1. Real Mode: effective address are used to access physical memory directly.

2. Virtual Mode: effective address are translated into physical address to access physical memory by the virtual-memory management hardware in microblaze.

The mode is controlled by the 18th bit (VM) of rmsr (Machine Status Register), as shown in fig. 1.

fig. 1 Machine Status Register

At the very beginning, the MMU runs in real mode, as the reset value of VM is 0. After OS properly set the first several entry in TLB (Translation Look-aside Buffer), the MMU will switch into Virtual Mode.

In virtual mode, whenever an address is requested, it goes through the following procedure:

To understand this procedure, we need to know so-called Translation Look-aside Buffer (TLB). TLB can be viewed as a cache for address translation. The translation between virtual address and physical address in virtual mode is done via a kind of mechanism called 2-level page table translation. In microblaze, the translation goes as follows:

There are certain addresses that are frequently accessed, the translation is stored in TLB, the same we do for data cache. If the requested data is not found in TLB, a TLB miss (similar as cache miss) is generated, followed by the page table translation and TLB update operation.

There are four registers used for accessing TLB from software: TLBLO, TLBHI, TLBX, and TLBSX.

TLBLO: Translation Look-Aside Buffer Low Register

TLBHI: Translation Look-Aside Buffer High Register

TLBX: Translation Look-Aside Buffer Index Register

TLBSX: Translation Look-Aside Buffer Search Index Register

All these registers are accessed via MFS and MTS instructions.

### Access TLB Entries

First of all, we need to know the TLB entry structure. A TLB entry can be accessed via TLBLO and TLBHI registers, with an index set at TLBX.

RPN (Real Page Number or Physical Page Number) is used to form physical address. Depending on the value of page size, certain bits of RPN are not used in physical address.

TAG (TLB-entry tag) is compared with the virtual memory address under control of SIZE.

SIZE (page Size) specifies page size.

There are 64 entries in the unified TLB in microblaze MMU architecture. So the INDEX field (bit 26 to 31, as shown below) of TLBX register is used as index of MMU entries. The field is also updated when TLBSX register is written with a virtual address and the virtual address is found in TLB entries.

Software can read and write unified TLB entries by using the TLBX register index (numbered 0 to 63) corresponding to one of the 64 entries in the TLB. The tag and data portions are read and written separately, so software must execute two MFS or MTS instructions to completely access an entry. The TLB is searched for a specific translation using the TLBSX register. TLBSX locates a translation using an effective address and loads the corresponding UTLB index into the TLBX register.

### Conclusion

All the above are the story about MMU architecture of microblaze. You may refer to xilinx document: MicroBlaze Processor Reference Guide for more detail explanation on microblaze and its instructions. The figures and information in this blog comes from the document directly. Linux kernel set up memory page mapping in arch/microblaze/head.S. I am going to talk about the codes in head.S in next blog in this series.

# what you need to Run Linux on XILINX FPGA

To run a kernel on a piece of hardware, you need several tools and a stable environment to do your job in.
Here is my tool lists, with a hyperlink so that you may easy to download them and repeat my job

### Environment

Let’s just begin with environment.
I recommend doing your entire job in Linux OS. To compile a linux kernel in a linux environment is the safest way to do, and fastest.
There are plenty of distributions for Linux out there for you to choose.
According to my experience with different distributions, here is my recommendation:

1. RHEL/CentOS 5.x or 6.x

Although in different names, RHEL (RedHat Enterprise Linux) and CentOS are basically the same. They share same rpm repositories, same kernel version, just named differently.
It is the environment that is most stable and hardly ever goes wrong. It may be a little bit slow to run on your laptop, but it’s the first choice for a beginner.

2. Ubuntu

I know a lot of people who are fond of Ubuntu, because of its glorious desktop. As more and more people are switching to it, it has a great support community on-line. You can easily find any solution to your problem. If you want a linux system on your personal laptop, it will be a good choice.

3. Debian

For people who have experience with Linux, I would like to recommend Debian. I am personally fond of Debian, because of its speed in compilation. Debian is the fastest system for software compilation. It takes one thirds time to compile a kernel than Fedora. However, as not many people work on it, you may need to solve your problems alone. So, if you are a linux guru, pick this one
Another important thing to mention is that you’d better have enough space to build your kernel source. Xilinx Tools may cost you about 10GB of your file system and the kernel source folder after compilation will cost 1GB. When you have more than one kernel sources in your system… that’s quite a lot space…

### Tool Chain

There is a saying that if you want to do a job right, you need to find proper tools. Here is what you need to build kernel on your FPGA board.

1. Xilinx Design Suite

That’s definitely what you need to build up an microblaze system on your FPGA and that’s the piece of hardware you will run you kernel on.
The version of Xilinx DS I recommended currently are 12.4 or 13.2.
Well, I have to say, the installation package gets bigger and bigger these days… You’d better have enough space for that.

2. Cross-compilation Tool Chain

As you are going to compile linux kernel for Xilinx Microblaze instead Intel CPU, you need a cross-platform compilation tool chain to do the work for you. The reason that they are named “cross-compilation” is that they themselves run on x86 or x64 systems while their output binaries run on other platforms.
For cross-compilation tool chain we use here, there are two places you may get them:


It is better to use “-pdflatexmx” while using chinese characters, as italic style is not available for chinese characters if you use other options.

2.2 Chinese Characters

CTeX includes a package for chinese characters called “CJK”. There are other packages for Chinese characters, while CJK is the one commonly used and is default in CTeX classes.

To use a CJK package, you should first include CJK in your .tex file as follows:
\include {CJK}

To use CJK font in document, before the text you may write:
\begin {CJK*} {GBK} {song}

This command stands for using CJK package GBK character map, font SongTi.
in GBK, the following fonts are available: song – SongTi, hei – HeiTi, kai – KaiTi, fs – FangSong.

We can use GB instead of BGK. Here we have more fonts:
gcfang – FangSong, gckai – KaiTi, gchei – HeiTi, gcsong – SongTi, gcwei – WeiBei, gchw – ZongYi, gcdls – LiShu.

\bfseries stands for bold style, \textsl stands for italic style.

2.3 CTEX classes

CTEX provides several document classes that support Chinese Language. ctexart is the article class with chinese support, ctexbook is the book class with Chinese support, ctexreport is the report class with chinese support. It is more convenient to use these classes while writing chinese documents. the reference for CTeX can be found at